Cadence and Samsung Foundry Expand Collaboration to Accelerate SoC, Chiplet, and 3D-IC Design for AI, Automotive, and Connectivity Applications
Cadence Design Systems, has announced a significant expansion of its strategic partnership with Samsung Foundry. This deepened collaboration includes a multi-year agreement that extends Cadence’s memory and interface IP portfolio across Samsung Foundry’s advanced process technologies—specifically SF4X, SF5A, and SF2P. Together, the companies aim to deliver optimized, high-performance, low-power system-on-chip (SoC), chiplet, and 3D-IC solutions for key growth sectors such as artificial intelligence (AI) data centers, advanced driver-assistance systems (ADAS), and next-generation RF connectivity.
This renewed partnership leverages Cadence’s comprehensive suite of AI-driven electronic design automation (EDA) tools, silicon IP, and system design technologies in combination with Samsung’s latest process node innovations. The result is an enhanced ecosystem that empowers customers to reduce time-to-market (TTM) and improve productivity while meeting the performance, power, and area (PPA) demands of next-generation semiconductor designs.
Broadening IP Coverage for Advanced Applications
At the heart of this expanded collaboration is a new multi-year IP agreement designed to provide cutting-edge interface and memory IP solutions targeting AI, high-performance computing (HPC), and automotive platforms. The extended IP portfolio on Samsung’s SF4X process node now includes:
- LPDDR6/5X PHY IP up to 14.4Gbps
- GDDR7 PHY at 36Gbps
- DDR5 IP supporting up to 9600 Mbps
- PCI Express® (PCIe®) 6.0, 5.0, and CXL 3.2
- Universal Chiplet Interconnect Express™ (UCIe™)-SP PHY at 32Gbps
- 10G multi-protocol PHY IP, supporting standards such as USB3.x, DisplayPort TX, PCIe 3.0, and SGMII
- LPDDR5X PHY at 8533Mbps, tuned specifically for automotive environments via the SF5A platform
- New 32G PCIe 5.0 PHY IP introduced for SF2P to support high-speed data transfer in AI and HPC use cases
This IP suite includes not only PHY (physical layer) components but also tightly integrated controller IPs, allowing customers to implement full subsystem silicon solutions with Cadence IP across multiple foundry nodes.
Certified Digital Design Flows for Samsung SF2P and Beyond
A cornerstone of this extended collaboration is the certification of Cadence’s full digital design flow on Samsung Foundry’s latest SF2P process. This includes support for:
- Samsung Hyper Cell methodology, which enables optimized power, performance, and area trade-offs
- Local Layout Effect (LLE) 2.0 timing analysis, allowing for enhanced layout-aware timing accuracy
This certification builds upon a collaborative Design Technology Co-Optimization (DTCO) initiative, ensuring Cadence digital tools are fully optimized for Samsung’s most advanced nodes. It ensures customers can confidently adopt Cadence tools for both current and upcoming Samsung technologies.
Hyung-Ock Kim, Vice President and Head of the Foundry Design Technology Team at Samsung Electronics, stated, “Cadence’s suite of digital tools from RTL to GDS is now certified for Samsung’s latest SF2P process node. Together, we are enabling advancements like Hyper Cell and LLE 2.0 and collaborating on analog migration, power integrity, and advanced thermal and warpage analyses for 3D-ICs, further enhanced by GPU acceleration.”
Analog Design Migration from 4nm to 2nm
As analog IP reuse becomes increasingly critical for reducing development time and cost, Cadence and Samsung have achieved successful automation of analog cell migration from 4nm to 2nm. This milestone enables customers to move legacy analog IP to the next-generation Samsung node without compromising design intent or performance.
By accelerating analog migration, customers can take advantage of advanced process benefits such as improved energy efficiency and transistor density while avoiding full custom re-development of analog blocks. This capability is essential in mixed-signal SoC designs where analog often lags digital in scalability.
Accelerating RF System Integration with Co-Design Flows
The two companies also introduced a joint co-design reference flow tailored for millimeter-wave (mmWave) RF applications. Using Samsung’s 14nm FinFET process, the reference flow supports the integration of front-end modules (FEM) and antenna-in-package (AiP) technologies—both critical for 5G and next-generation wireless communications.
The end-to-end flow supports:
- System-level budgeting
- RFIC/module/package co-design
- Post-layout simulation and verification
This RF chip/package co-design approach streamlines data handoff between development stages and reduces overall design turnaround time, a crucial advantage in rapidly evolving wireless markets.
Advanced Power Integrity Solutions for 3D-ICs
With the increasing adoption of 3D-IC architectures, managing power integrity across vertically stacked chips has become a significant challenge. To address this, Cadence and Samsung developed a comprehensive full-flow power integrity solution using:
- Cadence Voltus™ InsightAI, powered by machine learning to detect and fix IR-drop violations early in the flow
- Innovus™ Implementation System, optimized for 3D-IC floorplanning and routing
- Integrity™ 3D-IC Platform, which enables multi-die physical implementation and signoff
Applied to a high-speed CPU on Samsung’s SF2 node, Voltus InsightAI achieved resolution of 80–90% of IR-drop issues with minimal timing and power degradation. This demonstrates how advanced power analysis techniques can improve silicon reliability and performance predictability at scale.
Enabling Design Productivity and Faster Time-to-Market
According to Boyd Phelps, Senior Vice President and General Manager of the Silicon Solutions Group at Cadence, the renewed partnership is about more than just tools—it’s about empowering the next wave of innovation.
“We support a full portfolio of IP, subsystems, and chiplets on the Samsung Foundry process nodes,” said Phelps. “By combining Cadence’s AI-driven design and silicon solutions with Samsung’s advanced processes, we’re delivering the leading-edge technologies our mutual customers need to innovate and bring their products to market faster.”
This shared vision underlines the growing importance of foundry-tool provider alignment in the semiconductor industry, especially as complexity rises in advanced node and system-level design.
A Scalable, AI-Driven Design Ecosystem
As the semiconductor industry pivots toward AI-centric compute, chiplet-based architectures, and 3D integration, the Cadence-Samsung collaboration is poised to deliver scalable and efficient design enablement. By investing in certified flows, reusable IP, and tightly integrated co-design platforms, the two companies aim to meet the increasingly stringent demands of data-intensive applications across verticals.
With this expanded multi-year agreement, Samsung Foundry customers can expect enhanced support for emerging workloads, reduced design risk, and faster path to silicon for innovations in AI, automotive electronics, connectivity, and beyond.
